1. Field of the Invention
The present invention relates to R-2R circuits, and in particular to method and apparatus of calibrating an R-2R ladder circuit.
2. Description of Related Art
R-2R ladder circuits (hereafter R-2R ladder) are widely used for digital-to-analog converter (DAC). As depicted in FIG. 1, a prior art N-bit R-2R ladder 100 comprises (N−1) series resistors 121-123 of a nominal resistance R, N shunt resistors 111-114 of a nominal resistance 2R (which is twice as large as R) shunt to N control bits D[N−1]-D[0], respectively, and a termination resistor 130 of a nominal resistance 2R terminated to ground. For each control bit, the voltage level is set to a reference voltage VREF when the control bit is 1, and set to zero (i.e. grounded) when the control bit is 0. The output voltage VOUT is:VOUT=(D[N−1]·2N-1+D[N−2]·2N-2+ . . . +D[0]·20)·VREF/2N,orVOUT=(D[N−1]·2N-1+D[N−2]·2N-2+ . . . +D[0]·20)·VLSB,
which is linearly proportional to the number represented by the controlling code D[N−1:0], where VLSB=VREF/2N. In practice, a manufacturing process cannot guarantee a perfectly accurate resistance for each resistor. This effectively introduces an error to the output voltage VOUT. A particular specification of interest regarding a DAC's accuracy is the DNL (differential non-linearity). Ideally, the DAC's total output voltage will have an incremental change of VLSB in response to an incremental change of the number represented by the control code D[N−1:0]. DNL is defined as the difference between the actual incremental change and the ideal incremental change of the output voltage. The worst case DNL usually occurs when the control code makes an incremental change from where all bits of the control code, except for the MSB (most-significant bit), are 1 to where all bits of the control code, except for the MSB (most-significant bit), are 0.
What is desired is method of calibrating the DAC error.